Research Brief: The Mid-2026 Semiconductor Correction

A bilingual research brief for The Mid-2026 Semiconductor Correction: AI Infrastructure, Model Mis-Specification, and Memory as a Bottleneck Asset — SSRN Working Paper No. 7013899, Huang, Po-Sung (Sinclair), 2026. What the paper studies. The mid-2026 semiconductor correction generated two competing narratives: a “bubble-burst” reading grounded in legacy DRAM cycle models, and an “infrastructure repricing” reading grounded in bottleneck economics and AI capex fundamentals. The paper uses the divergence in analyst and retail commentary around Micron Technology as a case study in regime mis-specification — the application of a prior-cycle statistical model to a structurally transformed market environment. ...

August 2, 2026

Article 3 | How Deep Is the Moat? Reading TSMC, SK Hynix, and Micron Through Their SEC Filings

Customer prepayments, HBM margin structure, capital expenditure intensity — the numbers say more than the narratives do. Series: AI Compute Supply Chain | Part 3 of 5 By Po-Sung(Sinclair) Huang The previous article built a framework. This one tests it with documents. Before writing this piece, I set aside the analyst summaries and went to the source: TSMC’s 2024 20-F filed with the SEC on April 17, 2025; Micron’s most recent 10-K and two 10-Q filings; and SK Hynix earnings call transcripts for the past three quarters. ...

April 2, 2026